1. Field of the Invention
The invention generally relates to a memory device. More particularly, the invention relates to a memory device having a plurality of isolation structures and methods for fabricating the memory device.
2. Description of Related Art
Nowadays, a memory is typically a semiconductor device designed to store information or data. As the functionalities of computer microprocessors become more and more powerful, programs and operations executed by software are increasing correspondingly. As a consequence, the demand for high storage capacity memories is ever increasing. Among the plethora of memory products, the non-volatile memory allows repeated programming, readings, and erasures of data. Moreover, the stored data is retained even after power to the device is removed. In light of the aforementioned advantages, the non-volatile memory has become one of the most popular memory devices in personal computers and other electronic equipments.
Among non-volatile memories, the Electrically Erasable Programmable Read Only Memory (EEPROM) possesses the ability to store, read and erase data many times. Moreover, the EEPROM has the advantage that the stored data is not lost even after the system is power off. Therefore, the EEPROMs are widely used in the personal computers and electronic equipments. A typical EEPROM has a floating gate and a control gate fabricated from doped polysilicon. When the memory is being programmed, the electrons implanted into the floating gate are uniformly distributed in an entire polysilicon floating gate layer. However, if the tunnel oxide layer under the polysilicon floating gate layer has defects, it can easily cause a leakage current in the device, thereby affecting the reliability of the device.
Therefore, in order to solve the issue of current leakage in the EEPROM device, a conventional method utilizes stacked gate structures having a nonconductive charge storage layer to replace the polysilicon floating gate. Moreover, another advantage obtained from replacing the polysilicon floating gate with the charge storage layer is that the electrons are only locally stored in a neighboring portion of the channel region above the source region or the drain region while the device is programmed. Therefore, during the programming process, voltages can be respectively applied on the source region and the control gate of a terminal of the stacked gate structure. Furthermore, at the silicon nitride layer of the drain region near another terminal of the stacked gate structure, electrons are generated with a form of Gaussian distribution. Alternatively, voltages can be respectively applied on the drain region and the control gate of a terminal of the stacked gate structure. Moreover, at the silicon nitride layer of the source region near another terminal of the stacked gate structure, electrons are generated with a form of Gaussian distribution. In other words, by changing the voltages applied to the control gate and to either the source region or the drain region at the two sides, a single silicon nitride layer can have two storage regions that have electrons with a Gaussian distribution property, either one of the storage regions having electrons with the Gaussian distribution property, or none of the electrons stored in both storage regions. Hence, for this type of flash memory with the silicon nitride material replacing the floating goat, a single memory cell can be written with four different states. Therefore, this type of flash memory is considered a 2-bits-per-cell memory.
Conventionally, in order to increase the number of bits of a memory cell, a memory structure with a vertical memory cell is developed. This type of memory cell is a 4-bits-per-cell flash memory. However, between two adjacent vertical memory cells, the phenomenon of electron punching through happens easily. Hence, a significant leakage current in the memory structure is induced. Furthermore, since the vertical memory cells are too tightly disposed, disturbance is generated during programming.
Accordingly, needs exist for acquiring higher memory density while solving the aforementioned issues and maintaining the performance levels of the memory device.